Embedded Dynamic Random Access Memory (eDRAM) is a capacitor based memory integrated on the same die as an ASIC or processor. The cost-per-bit is typically higher than for stand-alone DRAM chips but in many applications the performance advantages of placing the eDRAM on the same chip as the processor outweighs the cost disadvantage compared with external memory.
Embedding memory on the ASIC or processor allows for much wider busses and higher operation speeds. And, due to much higher density of DRAM (in comparison to SRAM), larger amounts of memory can be installed on smaller chips. However, eDRAM requires additional fabrication processing steps, which raises cost, but the area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.
In current processing, moat isolation is required to prevent cross-talk of passive devices with active eDRAM arrays. In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive or conductive coupling from one circuit (eDRAM) to another circuit. However, in current technologies, a poly filled deep trench is followed by a poly recess process which cannot avoid Reactive Ion Etching (RIE) lag between a DRAM array and a moat isolation structure. Due to this RIE lag, the moat isolation region, with the larger critical dimension (CD), always has a deeper recess depth, which prevents the moat isolation by deep trench (DT) to substrate short. Also, the interfacial layer between the metal liner, e.g., TiN, and poly causes local recess depth variation at the DRAM array.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.